1. Field of the Invention
The present invention relates generally to chemical mechanical planarization (CMP) systems and techniques for improving the performance and effectiveness of CMP operations. Specifically, the present invention relates to CMP systems that implement polishing pads with improved post-conditioned surfaces.
2. Description of the Related Art
In the fabrication of semiconductor devices, there is a need to perform CMP operations, including topography planarization, polishing, buffing, and post-CMP wafer cleaning. Typically, integrated circuit devices are in the form of multi-level structures. At the substrate level, transistor devices are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistors to define the desired functional devices. As is well known, patterned conductive layers are insulated from other conductive layers by dielectric materials, such as silicon dioxide. At each metallization level and/or associated dielectric layer, there is a need to shape the metal interconnects and/or planarize the dielectric material. Without planarization, fabrication of additional metallization layers becomes substantially more difficult due to the higher variations in the surface topography. In other applications, metallization line patterns are formed in the dielectric material, and then metal CMP operations are performed to remove the overburden metallization.
CMP systems typically implement rotary, belt, or orbital material removal approaches, brush stations, and spin/rinse dryers in which belts, pads, or brushes are used to polish, buff, scrub, rinse, and dry one or both sides of a wafer. Slurry is used to assist the CMP operation. Slurry is most usually introduced onto a moving preparation surface, e.g., belt, pad, and the like, and distributed over the preparation surface as well as the surface of the semiconductor wafer being buffed, polished, or otherwise prepared by the CMP process. The distribution is generally accomplished by a combination of the motion of the preparation surface, the motion of the semiconductor wafer and the pressure created between the semiconductor wafer and the preparation surface.
An exemplary prior art CMP system 100 is illustrated in FIG. 1. The CMP system 100 is a belt-type system, so designated because the preparation surface is an endless polishing pad 108 mounted on two drums 114 which drive the polishing pad 108 in a rotational motion as indicated by polishing pad rotation directional arrows 116. A wafer 102 is mounted on a carrier 104, which rotates in a direction 106. The rotating wafer 102 is then applied against the rotating polishing pad 108 with a force F. Some CMP processes require a significant force F to be applied. A platen 112 is provided to stabilize the polishing pad 108 and to provide a surface onto which to apply the wafer 102. Typically, the platen 112 applies air to a gap between a top side of the platen 112 and the underside of the pad 108. Slurry 118, typically including an aqueous solution containing dispersed abrasive particles (e.g., SiO2, Al2O3, CeO2, etc.) is introduced upstream of the wafer 102.
Normally, the polishing pad 108 is composed of porous or fibrous materials. However, over a period of polishing, a residue consisting of abrasive particles of the slurry 118 and the by-products removed from the surface of the wafer 102 accumulates over the surface of the polishing pad 108, thus affecting the polishing rate and planarization efficiency. As a result, to maintain a stable material removal rate and high planarization efficiency, there is a need to condition the surface of the polishing pad 108.
As illustrated in FIG. 1, the polishing pad 108 is conditioned by applying a conditioning disk 122 onto the surface of the polishing pad 108. The conditioning disk 122 is mounted on a conditioning head 124 and moves along a track bar 123 across the polishing pad 108. Typically, the conditioning disk 122 includes a plurality of diamonds (not shown in this Figure) which are applied onto the surface of the polishing pad 108, thus removing the residue clogging the porous surface of the polishing pad 108. In addition to unclogging the pores, the conditioning disk 122 further removes the worn surface of the polishing pad 108, thus exposing a fresh layer of pad material. However, while pad conditioning positively effects the CMP process, it also affects the surface roughness of the polishing pad 108 thus degrading the planarization efficiency of the polishing pad 108.
The effects of conditioning on the polishing pad 108 can further be understood with reference to the enlarged, partial, cross-sectional view of the post-conditioned polishing pad 108 depicted in prior art FIG. 2A. As illustrated, a plurality of air pockets 108d are disbursed through out the surface of the polishing pad 108. Initially, a surface 108c of an unused polishing pad 108 is covered with air pockets 108d, which in a conditioning operation, are ripped open creating pores 108b and pad roughness features herein defined as asperities 108a. Thereafter, during the CMP operation, the slurry 118 is introduced onto the surface of the surface 108c of the polishing pad 108 such that the pores 108b and asperities 108a are covered with slurry 118. As shown, asperities 108a have different sizes and shapes.
Prior art FIG. 2B is an illustration of asperities 108a-1, 108a-2, and 108a-3, each having a different shape and size. As shown, the conditioning and roughening of the surface 108c of the polishing pad 108 creates the asperities 108a-1, 108a-2, and 108a-3 some of which significantly protrude above the surface 108c (e.g., asperity 108a-1). As discussed below with respect to FIGS. 3A-3C and 4A-4E, the formation of the asperities 108a, and specifically, the asperities that significantly protrude above the surface 108c are problematic during the CMP operation, as among others, the asperities 108a intrude into the depths of the features, thus degrading planarization uniformity.
The prior art FIG. 3A depicts an enlarged, partial, cross-sectional view of an ideal post-CMP oxide layer 250 having a heterogeneous top surface 250a. As shown, a plurality of copper metallization lines 254, 256, and 258 and a conductive via 251 have been fabricated in the oxide layer 250 implementing a dual damascene process. As is well known, in a dual damascene process, there is a need to perform a CMP operation so as to planarize and remove the over-burden copper material from over the heterogeneous top surface 250a. 
As shown, the copper metallization line 254 has two boundary sidewalls 255a and 255b. Ideally, sharp corners 254a and 254b should respectively be created at the intersection of boundary side-walls 255a and 255b with the corresponding oxide regions 250d and 250c of the heterogeneous top surface 250a. In a like manner, each of the copper metallization lines 256 and 258 has respective boundary side-walls 257a, 257b, and 259a with oxide regions 250c and 250b, respectively. Again, in theory, sharp corners 256a, 256b, and 258a should correspondingly be created at the intersection of each of the boundary sidewalls 257a, 257b, and 259a with the respective oxide regions 250c and 250b. Additionally, in theory, subsequent to the CMP operation, a top surface 254c, 256c, and 258c of each of the respective copper metallization lines 254, 256, and 258 should be in the same level as the heterogeneous top surface 250a. That is, it is expected that the thickness of the copper metallization lines 254, 256, and 258 stay the same throughout each of the copper metallization lines. However, this is not an accurate representative of a real post-CMP oxide layer.
Normally, the top surfaces of the copper metallization lines of heterogeneous oxide surfaces may not be flat. The top surfaces of the copper metallization lines defined in the same level as the oxide regions also commonly suffer from this problem. Based on experimental testing, the top surfaces of the copper metallization lines are some times defined below the level of the heterogeneous top surface 250a and the thickness of the copper metallization lines vary throughout each of the copper metallization lines. This occurs due to a phenomenon called xe2x80x9cdishingxe2x80x9d herein described as the thickness reduction of mechanically planarized copper metallization lines as a result of the moving polishing pad contacting the surface of the copper metallization lines under pressure.
The thickness reduction of copper metallization lines as opposed to oxide regions can be explained with the well-known Preston""s Equation. According to Preston""s Equation, Removal Rate=KpPV, where the removal rate of a material is a function of Polishing pressure (P) and Linear Velocity (V), with Kp being the Preston Coefficient, a constant determined by, among others, the properties of the material being planarized and the polishing slurry used. Accordingly, when the Kp of copper is significantly higher than the Kp of oxide, based on the Preston""s Equation, copper is polished faster than oxide, creating recessed regions in the copper metallization lines, thus exposing their sharp corners.
Additionally, as a result of dishing, the intersections of the copper metallization lines and oxide regions are rounded corners due to a phenomenon called xe2x80x9ccorner rounding.xe2x80x9d Typically, the exposure of the sharp corners caused by dishing results in the removal of the oxide adjacent to the exposed corners. Furthermore, where the oxide regions are narrow, the high selectivity of Kp of copper over Kp of oxide causes the narrow oxide regions to be removed at the same removal rate of copper. As a result, in narrow oxide spacings, when the extensions of corner rounding on both sides of oxide spacings overlap, the so-called xe2x80x9cdielectric erosionxe2x80x9d is caused.
Generally, dishing, corner rounding, and dielectric erosion occur as a result of the moving polishing pad 108 and thus the asperities 108a contacting the heterogeneous top surface. In fact, the key contributor of these negative effects are the asperities 108a, specifically, the protruding asperities 108a-1. For instance, the asperities 108a intrude into the depths of the copper metallization lines causing the recesses, thus affecting feature performance. Additionally, the asperities 108a are significantly larger in size than the sharp corners created at the intersections of the boundary sidewalls with the oxide regions. Consequently, the asperities 108a, and particularly the protruding asperities 108a-1, increase the removal of the adjacent oxide, aggravating the effects of corner rounding and dielectric erosion.
These phenomenon are illustrated in the enlarged, partial, cross-sectional view of a real post-CMP oxide layer 250xe2x80x2 of prior art FIG. 3B. As shown, due to the effects of dishing and corner rounding, the thickness of the copper metallization lines 254xe2x80x2, 256xe2x80x2, and 258xe2x80x2 of post-CMP oxide layer 250xe2x80x2 varies throughout each of the copper metallization lines. For instance, as opposed to the copper metallization line 254 of FIG. 3A in which the top surface 254c is flat, as a result of dishing and corner rounding, a top surface of the copper metallization line 254xe2x80x2 includes a plurality of top recessed regions 254c-1xe2x80x2, 254c-2xe2x80x2, and 254c-3xe2x80x2. Similarly, each of the copper metallization lines 256 and 258 has a top recessed region 256cxe2x80x2 and 258cxe2x80x2, respectively. Additionally, rounded corners 254axe2x80x2, 254bxe2x80x2, 256axe2x80x2, 256bxe2x80x2, and 258axe2x80x2 have been respectively formed at the intersections of the boundary sidewalls 255axe2x80x2, 255bxe2x80x2, 257axe2x80x2, 257bxe2x80x2, and 259axe2x80x2 with the oxide regions 250dxe2x80x2, 250cxe2x80x2, and 250bxe2x80x2, respectively. Furthermore, while the wide oxide region 250cxe2x80x2 has rounded corners, it has remained at about the same level as the heterogeneous top surface 250axe2x80x2 of the oxide layer 250xe2x80x2. However, the same thing is not true with respect to the narrow oxide region 250bxe2x80x2. In fact, the corner rounding has lead to the significant erosion of the narrow oxide region 250bxe2x80x2 such that it now falls below the heterogeneous top surface 250axe2x80x2. 
The concerted effects of dishing and corner rounding on a wide copper metallization line and its adjacent wide oxide region can further be understood with respect to the prior art FIG. 3C. As shown, the thickness of the copper metallization line 254xe2x80x2 varies throughout the copper metallization line. Specifically, as a result of dishing and corner rounding, three top recessed regions 254c-1xe2x80x2, 254c-2xe2x80x2, and 254c-3xe2x80x2 have been formed. Additionally, each of the top recessed regions 254c-1, 254c-2, and 254c-3 falls below the top surface 254c of the copper metallization line 254 as well as the oxide region 250c. Furthermore, due to corner rounding, the sharp corners 254b and 254a have been replaced by rounded corners.
Simply stated, the dishing effect in copper metallization lines ultimately results in corner rounding. That is, first, dishing causes the top recessed region 254c-1 to be formed, which in turn, results in the exposure of the sharp corners 254b and 254a. Once exposed, the application of the polishing pad 108 and the asperities 108a onto the sharp corners 254b and 254a results in the oxide removal from the intersection of the boundary sidewalls 255b and 255a and oxide regions 250c and 250d, respectively, and therefore, in rounding of the sharp corners 254b and 254a. However, the rounding of the sharp corners 254b and 254a itself leads to the formation of top recessed regions 254c-2 and 254c-3, thus exposing more of the sharp corners 254b and 254a. Consequently, the continuous application of the polishing pad 108 and the asperities 108a causes additional oxide to be removed, thus deepening the top recessed regions 254c-2 and 254c-3. In this manner, a cycle is created. Nonetheless, as a result of the oxide region 250c being wide, the resulting oxide region 250cxe2x80x2 does not entirely fall below the level of the heterogeneous top surface 250axe2x80x2. 
In contrast, where the oxide region is narrow, the corner rounding and thus dielectric erosion cause the resulting oxide region to fall below the level of the heterogeneous top surface 250axe2x80x2. This is illustrated in the enlarged, partial, cross-sectional view of the post-CMP dielectric layer 250xe2x80x2 of prior art FIG. 3D, depicting the dielectric erosion of a distant xe2x80x9cHxe2x80x9d of the oxide region 250b. As shown, the high selectivity of Kp of copper over Kp of oxide has caused the narrow oxide region 250b to be removed at the same removal rate as copper. As such, the resulting oxide region 250bxe2x80x2 is defined below the level of the heterogeneous top surface 250axe2x80x2. 
Corner rounding and the related dielectric erosion can further be understood with respect to the prior art FIGS. 4A-4E illustrating the dishing effect being maturated into the corner rounding effect. As shown in the enlarged, partial, cross-sectional view of FIG. 4A, while the polishing pad 108 is static, the polishing pad 108 rests upon a portion of the top surface 254c of the copper metallization line 254, the sharp corner 254b, and the oxide region 250c. While static, the polishing pad 108 does not engage the boundary sidewall 255b, and the polishing pad 108 significantly protrudes above the boundary sidewall 255b and the top surface 254c. 
Once the polishing pad 108 starts to move in the movement direction 262, as depicted in FIG. 2B, the Polishing pad 108 intrudes, thus contacting the upper portion of the boundary sidewall 255b. As shown in FIG. 4C, while moving, the polishing pad 108, and thus the asperities 108a engage the upper portion of the sidewall 255b and the sharp corner 254b, creating a rounded corner 254b-1xe2x80x2. In this manner, corner rounding causes oxide removal along the upper portion of a boundary sidewall 255b-1xe2x80x2, the rounded corner 254b-1xe2x80x2, and an oxide region 250c-1xe2x80x2. As illustrated in FIG. 4D, due to corner rounding and dielectric erosion, the resulting boundary sidewall 255b-2xe2x80x2 as well as the resulting oxide region 250c-2xe2x80x2 are shorter than the boundary sidewall 255b and the oxide region 250c, respectively. Furthermore, as shown, a rounded corner 254b-2xe2x80x2 has been formed.
The origin of corner rounding and dielectric erosion can further be understood in reference to prior art FIG. 4E. As shown, once the polishing pad 108 deforms as it comes into contact with the upper portion of the boundary sidewall 255b, the kinetic energy of the relative motion of the polishing pad 108 is converted into pad/feature corner interaction energy, thus creating a plurality of force vectors F1-F7. Depending on their distance from the sharp corner 254b, the sizes of the force vectors F1-F7 vary. The largest force vector F1 is the force vector closest to the sharp corner 254b, and is created at a point the polishing pad 108 engages the sharp corner 254b most significantly. As a result, corner rounding and dielectric erosion are most pronounced in the oxide region adjacent to the sharp corner 254b. Comparatively, the smallest force vector F7 is the force vector farthest removed from the sharp corner 254b, and is created where the pad engagement is least significant, thus creating the least degree of corner rounding. Hence, as the polishing pad engages the sharp corners, the CMP of the oxide layer having heterogeneous surfaces results in copper metallization lines loss as well as oxide erosion.
Starting from the first copper metallization layer, the negative effects of dishing, corner rounding, and dielectric erosion mainly caused by the polishing pad roughness features and asperities result in an uneven post-CMP surface topography. This unevenness of surface topography escalates into a more varied and complicated topography as additional layers are formed and planarized. Additionally, because the metallization content in each line is not uniform, it is not possible to use modeling parameters to define how a device will function as a finished product. As can be appreciated, defective semiconductor structures ultimately lead to the discarding of valuable wafers, thus reducing costly throughput.
In view of the foregoing, a need therefore exists in the art for an assembly for use in a chemical mechanical planarization (CMP) system that maximizes the planarization uniformity by improving the polishing pad performance while minimizing the damaging effects of dishing, corner rounding, and dielectric erosion.
Broadly speaking, the present invention fills these needs by apparatuses and related methods for ironing a post-conditioned surface of a polishing pad, thus minimizing the damaging effects of dishing, corner rounding, and dielectric erosion caused by the pad surface roughness features. Preferably, the CMP system is designed to implement an ironing assembly to flatten the pad surface roughness features formed on a post-conditioned surface of the polishing pad. The pad surface roughness features are herein defined as xe2x80x9casperities.xe2x80x9d In preferred embodiments, the ironed asperities are flattened such that they lay substantially at the same level as the surface of the post-conditioned polishing pad. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, a method for smoothing a surface of a polishing pad previously used in planarizing a surface of a substrate in a chemical mechanical planarization (CMP) system is disclosed. The method starts by conditioning the surface of the polishing pad so as to create a post-conditioned surface having an asperity. The post-conditioned surface of the polishing pad is then ironed, thus compressing the asperity onto the post-conditioned surface of the polishing pad such that the asperity lays substantially flat against the post-conditioned surface of the polishing pad.
In another embodiment, a method for smoothing a surface of a polishing pad previously used in planarizing a surface of a substrate in a chemical mechanical planarization (CMP) system is disclosed. The method starts by conditioning the surface of the polishing pad so as to create a post-conditioned surface having a plurality of asperities. The post-conditioned surface of the polishing pad is then ironed, thus compressing the plurality of asperities onto the post-conditioned surface of the polishing pad such that the plurality of asperities lay substantially flat against the post-conditioned surface of the polishing pad.
In still a further embodiment, an ironing assembly for use in a chemical mechanical planarization (CMP) apparatus is disclosed. The ironing assembly is designed to be used over a polishing pad having a post-conditioned surface that includes a plurality of asperities. The ironing assembly includes an ironing disk, an ironing head and an ironing track bar. The ironing disk has a contact surface and is oriented over the polishing pad such that the contact surface of the ironing disk is applied onto the post-conditioned surface of the polishing pad. The ironing head has a base coupled to the track bar and a bottom surface coupled to a non-contact surface of the ironing disk. The ironing disk is applied onto the post-conditioned surface of the polishing pad as the ironing base moves along the ironing track bar and the polishing pad moves along a direction of rotation. The application of the contact surface of the ironing disk onto the post-conditioned surface acts to at least partially flatten the plurality of asperities.
In yet another embodiment, an ironing assembly for use in chemical mechanical planarization (CMP) is disclosed. The ironing assembly is designed for use over a linear polishing pad having a plurality of asperities and applied slurry. The ironing assembly includes an ironing disk having a contact surface. The ironing disk is oriented over the linear polishing pad such that the contact surface of the ironing disk can be applied over the surface of the linear polishing pad, thus at least partially flattening the plurality of asperities before planarizing a semiconductor wafer surface over the linear polishing pad.
In yet another embodiment, an apparatus for use in a chemical mechanical planarization (CMP) system so as to improve the planarization uniformity of the CMP system is disclosed. The apparatus includes a polishing pad previously used in polishing a surface of a substrate, a track bar, an arm, a conditioning assembly, and an ironing assembly. The arm has a first point and a second point that is separate from the first point such that the arm is coupled to the track bar at the first point. The conditioning assembly has a conditioning base that is coupled to the arm at a conditioning point defined between the first point and the second point. The conditioning assembly is configured to condition the polishing pad so as to create a post-conditioned surface having a plurality of asperities. The ironing assembly has an ironing base that is coupled to the arm at an ironing point defined between the first point and the second point. The conditioning point is configured to precede the ironing point.
The advantages of the present invention are numerous. Most notably, by significantly reducing the damaging effects of dishing, corner rounding, and dielectric erosion caused by the asperities on the surface of the post-conditioned polishing pad, the ironing system of the present invention significantly improves the planarization uniformity of the polishing pad. In eliminating these negative effects, the ironing system of the present invention extensively contributes to successfully implementing modeling parameters to assess the quality of a finished multi-level semiconductor device having copper metallization lines. In this manner, better quality semiconductor devices can be fabricated thus reducing the number of defective wafers, which ultimately increases the throughput.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.